Informatics Publishing Limited

S. Subathradevi ¹, C. Vennila ²

Affiliations
1 A.P. Department of ECE, Anna University, BIT Campus Tiruchirappalli, Tamil Nadu, IN
2 Department of ECE, Saranathan College of Engineering, Tiruchirappalli, Tamil Nadu, IN

Abstract

In VLSI design of system configuration, the important parameter speed is playing a vital role in the design which is purely determined by the delay of the design. In the delay of the design is arrived by design delay and routing i.e. path delay. Nowadays in the design, the path or routing delay dominates more due to miniaturization of the design. During earlier days design delay dominates more. Because of scaling in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay in turn optimized speed in trade of with area. In the proposed work, by reviewing different architecture was constructed with different basic module in order to achieve optimized delay which is realized using verilog HDL.

Keywords

Architecture, Distributed Arithmetic, FIR Filter, Parallel Processing, Routing Delay, VLSI Design

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S. Subathradevi ¹, C. Vennila ²

Affiliations
1 A. P. Department of ECE, Anna University, BIT Campus, Tiruchirappalli – 600025, Tamil Nadu, IN
2 Department of ECE, Saranathan College of Engineering, Tiruchirappalli – 620012, TamilNadu, IN

Abstract

In VLSI design of system configuration, among the three important parameters of speed, area and power, the speed is purely determined by the delay of the design. In the delay of the design the design delay is contributed by gate delay and routing i.e. path delay. Nowadays in the design, the path or routing delay dominates more towards the design delay compare to the earlier days where gate delay dominates more towards the design delay. Because of scaling in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay or desired speed of the design with the reduced area. In this work, by studying different architectures constructed with different basic module for binary array multiplier contributes towards the routing delay which can be realized to result in reduced delay.

Keywords

Architecture, Binary Array Multiplier, Path Delay, Routing Delay, VLSI

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S. Venkatasubramanian ¹, A. Suhasini ², C. Vennila ³

Affiliations
1 Department Computer Science and Engineering, Saranathan College of Engineering, Trichy, Tamil Nadu, IN
2 Department Computer Science and Engineering, Annamalai University, Tamil Nadu, IN
3 Department of Electronics and Communications Engineering, Saranathan College of Engineering, Trichy, Tamil Nadu, IN

Abstract

Mobile ad hoc networks (MANETs) is an infrastructure-less network, which is self-organizing, self-configuring and dynamic. The traditional routing protocol is not efficient against the routing challenges. The traditional MANET routing mechanisms involve overhearing, retransmission, and idle listening, which consume high energy. The main obstacles for MANET are end-to-end delay, energy consumption, and packet collision problems. The enhancement of network lifetime and communication performance is still a challenging task. This paper proposes a Ticket-ID zone manager routing protocol (TID-ZMGR) with sleep scheduling for MANETS. The proposed system consists of a zone routing system that is effective in load balancing and energy-efficient. In the proposed approach, nodes in the network are grouped as zones with a zone leader (ZL). The ZL is the node with higher efficiency in terms of energy, link quality, connectivity, and distances. The TID-ZMGR follows a multipath mechanism for balancing the load, and traffic is controlled by distributing the path from source to destination. The implementation of an adaptive sleep duty cycling approach ensures error-free communication around the network. Additionally, the adaptive sleep duty cycling approach increases the overall accuracy by saving the power on border nodes. The efficiency of the proposed work is proved by the comparison work carried out between Ticket-ID Based Routing management system (TID-BRM) Zone-based Routing with Parallel Collision Guided Broadcasting Protocol (ZCG) and Distance aware Zone Routing Protocol (DZRP) with TID-ZMGR. Experimental work evaluation metrics are zonal leader changes, energy consumptions, and network lifetime. Simulation result shows proposed mechanism achieves minimum energy consumption with improved output on throughput and packet delivery ratio.

Keywords

MANET, ZL, ZCG, DZRP, TID-ZMGR.

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